Foundry Meeting

Semiconductor Foundry Access by US Academic Researchers in Micro- and Nano- Circuits and Systems (NSF workshop), December 16, 2020

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To evaluate academic needs for access to semiconductor foundry and associated support infrastructure for design tools and IP solutions, and brainstorm ways to provide such access and support to US academic researchers.


The MOSIS program that started around 1981 unleashed the innovation of circuit designers and enabled circuit research to proceed in parallel with device technology research. Fast forward 40 years, the needs of today are drastically different from decades ago. Design innovations are now strongly coupled with chip-/system-architecture innovations; circuit innovations often derive from the use of new device technologies; and, device technology innovations are driven by application needs and require circuit/architecture level demonstrations to be relevant.

Meeting Focus

Discussions at this forum are expected to center around three major issues.

  1. Foundry access to advanced technologies by designers
    1. Access to advanced technology nodes for standard CMOS. Today, advanced technology nodes can mean 12-nm, 7-nm and beyond.
    2. Access to emerging technologies that are still in development or early customer engagement phase. Examples of these include MRAM on CMOS logic, RRAM on CMOS logic, or carbon nanotube FETs, Ferroelectric FETs and RRAM.
    3. Access to new integration of technologies (such as chiplets with active interposers, 3D using TSVs, bonding, monolithic 3D integration of carbon nanotube FETs and RRAM)
    4. Access of More-than-Moore (or specialty) technologies. Examples of these include CMOS image sensor, GaN devices on silicon, BCD (bipolar-CMOS-DMOS) technology
  2. Foundry access for creating new technology demonstrators
    1. University clean rooms (such as those supported by the NSF NNCI) today do not have the capability to fabricate state-of-the-art transistors, nor do they have the capability to yield an enough number of devices for meaningful circuit demonstrations. Access to full-wafer or Multi-Project-Wafer (MPW) in standard CMOS technology is required with the goal of additional fabrication to integrate new devices on the CMOS wafers. The new devices are typically the innovations of academic research. The standard CMOS provides control, sense, and measurement circuitry needed to address the novel devices.
  3. Access to design ecosystem (EDA tools, design flows, IP blocks)
    1. Many chip-level innovations today involve architecture- and system-level optimizations. For end-to-end demonstrations (that are generally complex), access to state-of-the-art EDA tools (e.g., high-level synthesis, logic synthesis, physical design, power optimization, signal integrity) and reference design flows, calibrated to advanced technologies, is crucial. Very few academic groups have such capabilities.
    2. In addition, for system-level demonstrations, access to IP blocks (e.g., memory interfaces) becomes important -- not easily available to academics.
    3. These challenges become even more severe for new architectures enabled by new technologies (such as 3D, chiplets with active interposers), requiring new tools and design flows (e.g., for partitioning, thermal analysis).
    4. Much of the disruptive innovation in EDA tools originates from academia, benefiting from open-source sharing of community-wide development. In contrast, open-source development efforts lack the resources available to large EDA companies in delivering industry-strength solutions. This continues to be a controversial topic calling for discussion and input from the various stakeholders.

Meeting Schedule

The meeting was held onĀ Wednesday, December 16th. The detailed schedule is listed here.